1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and, more particularly, to a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same.
2. Description of the Related Art
A nonvolatile memory such as a flash memory can maintain data until a removal operation is performed after the data are input. Therefore, the nonvolatile memory does not require a refresh operation so that power consumption can be reduced compared to a volatile memory such as a Dynamic Random Access Memory (DRAM).
However, a high voltage is typically required to be applied to the nonvolatile memory in order to write and erase the data in a cell, and a separate and reliable storing space is required to maintain the data. Thus, a semiconductor device having the nonvolatile memory cell consists of regions for applying different voltages such as a region for applying a high voltage to write and erase the data, a region for applying a low voltage for implementing high-speed operation of the semiconductor device, and a region for applying a medium voltage like an I/O circuit region having a voltage between the high and low voltages as well as a cell region.
The nonvolatile memory cell may be classified as a floating gate type or a floating trap type according to the storing space. The floating trap type nonvolatile memory cell stores charges in a trap formed in a non-conductive charge storing layer, while the floating gate type nonvolatile memory cell stores the charges in a polysilicon layer. A representative SONOS (Silicon Oxide Nitride Oxide Semiconductor) cell of the floating trap type nonvolatile memory cell has a gate pattern composed of a tunnel oxide layer, a silicon nitride layer as a charge storing layer, a blocking oxide layer and a conductive layer deposited on a silicon substrate sequentially.
In the process of manufacturing the semiconductor device having the SONOS cell, the blocking oxide layer is preferably formed of a CVD oxide layer, and all of a high voltage gate oxide layer formed on the high voltage region, a medium voltage gate oxide layer formed on the medium voltage region, and a low voltage gate oxide formed on the low voltage region are formed with different thicknesses. The thickest high voltage gate oxide layer may be formed of a thermal oxide layer only. But, in this case, the time duration of forming the high voltage gate oxide layer is too long, and, as a result, the impurity profile in the substrate can be changed significantly. Also, the thickest high voltage gate oxide layer may be formed of a CVD oxide layer only. But, in this case, in consideration of the nature of the CVD oxide layer formed on an entire surface of the substrate, it also causes the thickness of the blocking oxide layer to be increased. In addition, the blocking oxide layer and the high voltage gate oxide layer, which are formed of the deposited oxide layer, are easily etched in a subsequent wet-etching process, thereby making it difficult to control the final thickness thereof.